In recent years, NAND flash memory which is a large-capacity and low-cost nonvolatile semiconductor memory device has been used as storage memory such as memory cards and semiconductor disks, e.g., SSDs (Solid State Disks); and applications and markets are growing. There is a need for even larger capacities and lower costs of storage memory; and downscaling of the patterning dimensions of NAND flash memory has progressed to realize larger capacities and lower costs.
Known methods of forming an interconnect pattern having a line-and-space (L/S) configuration on a substrate include a damascene process in which a conductive material is filled into a trench made in an insulating film. Known methods of forming an L/S pattern having an ultra-fine arrangement period exceeding the resolution limit of the lithography include a so-called sidewall method. By combining the sidewall method and the damascene process, an interconnect pattern having an ultra-fine arrangement period can be formed. In other words, a pattern having an L/S configuration is formed on an insulating film using lithography; slimming of the pattern is performed; and sidewalls are formed on the side faces thereof. Thereby, sidewalls having an ultra-fine arrangement period exceeding the resolution limit of the lithography are formed. Then, etching is performed using the sidewalls as a mask to make trenches in the insulating film. Interconnects are formed in the trenches by filling a conductive material into the trenches and planarizing the upper face using CMP (chemical mechanical polishing) and the like. In such a case, the interconnects are formed in the regions directly under the regions between the sidewalls; and the regions directly under the sidewalls are the regions between the interconnects.